Functional Performance
summary
Benchmarks show linear reads hitting caches at 0.8 ns per element while dependent random loads jump to ~90 ns, exposing prefetch, TLB and parallel miss limits; queueing math (Little’s law) and Universal Scalability Law quantify contention and coherence costs across many cores (dozens on modern Ryzen chips). Implementation choices: UDP with a log buffer (monotonic, memory-sequential frames, negative-length marker and tombstones) and lock-free tail increments power the Aeron messaging design, reducing GC and coherence pain while producing strong eventual consistency.
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chapters (8)
- 0:00Start
- 1:50Functional Performance
- 20:48Systems Engineering
- 22:12What are the normal approaches?
- 27:08Garbage Collection Hell
- 34:11Concurrent Publication?
- 35:47What's in a header?
- 36:13What if a Publisher dies mid operation?
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