SYCL: Open Your Code to More Hardware Choices
summary
Explains using SYCL 2020 and Intel’s DPC++ compiler to run a real-world stencil: the EasyWave tsunami simulation is ported from CUDA/OpenMP, runs on Intel CPUs and GPUs, AMD and NVIDIA GPUs and even an FPGA (FPGA needs extra tuning), and shows performance within about 5% of native CUDA on NVIDIA. Covers buffer/accessor vs unified shared memory, queues/events, nd_range control, and backend choices (Level Zero, OpenCL, CUDA, HIP) with AOT and JIT options.
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chapters (30)
- 0:00Start
- 3:43The Difference between Sql and Dpc Plus Plus
- 7:46Community Extensions
- 9:15Intel Compiler
- 11:44Parallel Programming Models
- 13:47Skeleton of a Sql Application
- 14:53Application Scopes
- 18:05Buffer Memory Model
- 19:51Buffer Classes
- 21:23Runtime Environment Variables
- 23:37Data Dependencies
- 25:16Kernels in Parallel
- 26:10The Dependency Graph
- 28:01Lambda Function
- 28:53Template Deduction
- 30:39Work Groups
- 33:56Optimization Hints
- 39:03Synchronization within Kernel
- 40:10Host Accessors
- 41:40Buffer Destruction Synchronization
- 42:18The Unified Shared Memory Approach
- 45:31Synchronous Exceptions
- 46:49Under the Hood
- 48:51Ahead of Time Compilation Flow
- 51:21Plugin Interface Layer
- 53:06Unified Shared Memory
- 54:50Explicit Data Movement Mode
- 56:33Implicit Data Movement Mode
- 57:03Stencil Code
- 58:34Useful Links
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